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| K4B1G04(08/16)46D 1Gb DDR3 SDRAM 1Gb D-die DDR3 SDRAM Specification 82 / 100 FBGA with Lead-Free & Halogen-Free (RoHS Compliant) CAUTION : * This document includes some items still under discussion in JEDEC. * Therefore, those may be changed without pre-notice based on JEDEC progress. * And it's highly recommended not to send the spec without Samsung's permission. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Page 1 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM History - First release - Changed Current Specification - Corrected Typo Revision History Revision 1.0 1.1 Month March August Year 2008 2008 Page 2 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM Table Contents 1.0 Ordering Information ................................................................................................................... 5 2.0 Key Features ................................................................................................................................ 5 3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6 3.1 x4 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls) ..................... 6 3.2 x8 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls) ..................... 7 3.3 x16 Package Pinout (Top view) : 100ball FBGA Package(96balls + 4 balls of support balls) ................. 8 3.4 FBGA Package Dimension (x4/x8) ................................................................................................. 9 3.5 FBGA Package Dimension (x16) .................................................................................................. 10 4.0 Input/Output Functional Description ....................................................................................... 11 5.0 DDR3 SDRAM Addressing ........................................................................................................ 12 6.0 Absolute Maximum Ratings ...................................................................................................... 13 6.1 Absolute Maximum DC Ratings ................................................................................................... 13 6.2 DRAM Component Operating Temperature Range ......................................................................... 13 7.0 AC & DC Operating Conditions ................................................................................................ 13 7.1 Recommended DC operating Conditions (SSTL_1.5) ...................................................................... 13 8.0 AC & DC Input Measurement Levels ........................................................................................ 14 8.1 AC and DC Logic input levels for single-ended signals .................................................................. 14 8.2 VREF Tolerances ........................................................................................................................ 15 8.3 AC and DC Logic Input Levels for Ditterential Signals .................................................................... 16 8.3.1 Differential signal definition ................................................................................................ 16 8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .............................. 16 8.3.3 Single-ended requirements for differential signals ................................................................. 17 8.4 Differential Input Cross Point Voltage .......................................................................................... 18 8.5 Slew Rate Definition for Single Ended Input Signals ...................................................................... 18 8.6 Slew rate definition for Differential Input Signals ........................................................................... 18 9.0 AC and DC Output Measurement Levels.................................................................................. 19 9.1 Single Ended AC and DC Output Levels ....................................................................................... 19 9.2 Differential AC and DC Output Levels .......................................................................................... 19 9.3.Single Ended Output Slew Rate................................................................................................... 19 9.4 Differential Output Slew Rate ...................................................................................................... 20 9.5 Reference Load for AC Timing and Output Slew Rate ..................................................................... 20 9.6 Overshoot/Undershoot Specification ........................................................................................... 21 9.6.1 Address and Control Overshoot and Undershoot specifications ............................................. 21 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications ................................. 21 9.7 34 ohm Output Driver DC Electrical Characteristics ....................................................................... 22 9.7.1 Output Drive Temperature and Voltage sensitivity ................................................................. 23 9.8 On-Die Termination (ODT) Levels and I-V Characteristics ............................................................... 23 9.8.1 ODT DC electrical characteristics ........................................................................................ 24 9.8.2 ODT Temperature and Voltage sensitivity ............................................................................. 25 9.9 ODT Timing Definitions .............................................................................................................. 26 9.9.1 Test Load for ODT Timings ................................................................................................. 26 9.9.2 ODT Timing Definition ........................................................................................................ 26 Page 3 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM 10.0 Idd Specification Parameters and Test Conditions .............................................................. 29 10.1 IDD Measurement Conditions ................................................................................................... 29 10.2 IDD Specifications definition .................................................................................................... 29 11.0 1Gb DDR3 SDRAM D-die IDD Spec Table .............................................................................. 38 12.0 Input/Output Capacitance ....................................................................................................... 40 13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 .............................. 41 13.1 Clock specification ................................................................................................................. 41 13.1.1 Definition for tCK (avg) ................................................................................................... 41 13.1.2 Definition for tCK (abs) ................................................................................................... 41 13.1.3 Definition for tCH(avg) and tCL(avg) ................................................................................. 41 13.1.4 Definition for note for tJIT(per), tJIT(per,lck) ..................................................................... 41 13.1.5 Definition for tJIT(cc), tJIT(cc,lck) .................................................................................... 41 13.1.6 Definition for tERR(nper) ................................................................................................ 41 13.2 Refresh Parameters by Device Density ...................................................................................... 42 13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ............................................ 42 13.3.1 Speed Bin Table Notes ................................................................................................... 44 14.0 Timing Parameters by Speed Grade ...................................................................................... 45 14.1 Jitter Notes ............................................................................................................................ 48 14.2 Timing Parameter Notes .......................................................................................................... 49 14.3 Address / Command Setup, Hold and Derating: .......................................................................... 50 14.4 Data Setup, Hold and Slew Rate Derating: ................................................................................. 56 Page 4 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1.0 Ordering Information [ Table 1 ] Samsung 1Gb DDR3 D-die ordering information table Organization 256Mx4 128Mx8 64Mx16 DDR3-800 (6-6-6) K4B1G0446D-HCF7 K4B1G0846D-HCF7 K4B1G1646D-HCF7 DDR3-1066 (7-7-7) K4B1G0446D-HCF8 K4B1G0846D-HCF8 K4B1G1646D-HCF8 DDR3-1333 (9-9-9) K4B1G0446D-HCH9 K4B1G0846D-HCH9 K4B1G1646D-HCH9 1Gb DDR3 SDRAM DDR3-1600 TBD TBD TBD Package 82 FBGA 82 FBGA 100 FBGA Note : 1. Speed bin is in order of CL-tRCD-tRP. 2. x4/x8/x16 Package - including 4 support balls 2.0 Key Features [ Table 2 ] 1Gb DDR3 D-die Speed bins Speed tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) DDR3-800 6-6-6 2.5 6 15 15 37.5 52.5 DDR3-1066 7-7-7 1.875 7 13.125 13.125 37.5 50.625 DDR3-1333 9-9-9 1.5 9 13.5 13.5 36 49.5 DDR3-1600 TBD TBD TBD TBD TBD TBD TBD Unit ns nCK ns ns ns ns * JEDEC standard 1.5V 0.075V Power Supply * VDDQ = 1.5V 0.075V * 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin * 8 Banks * Posted CAS * Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10 * Programmable Additive Latency: 0, CL-2 or CL-1 clock * Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600) * 8-bit pre-fetch * Burst Length: 8 (Interleave without any limit, sequential with starting address "000" only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] * Bi-directional Differential Data-Strobe * Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) * On Die Termination using ODT pin * Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95 C * Asynchronous Reset * Package : 82 balls FBGA - x4/x8 (with 4 support balls) 100 balls FBGA - x16 (with 4 support balls) * All of Lead-Free products are compliant for RoHS * All of products are Halogen-free The 1Gb DDR3 SDRAM D-die is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V 0.075V power supply and 1.5V 0.075V VDDQ. The 1Gb DDR3 D-die device is available in 82ball FBGAs(x4/x8) and 100ball FBGA(x16) Note : 1. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in "DDR3 SDRAM Device Operation & Timing Diagram". Page 5 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 3.0 Package pinout/Mechanical Dimension & Addressing 1Gb DDR3 SDRAM 3.1 x4 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls) 1 A B C D E F G H J K L M N NC NC 2 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 3 VDD VSSQ DQ2 NC VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 4 NC DQ0 DQS DQS NC RAS CAS WE BA2 A0 A2 A9 A13 5 6 7 8 NC DM DQ1 VDD NC CK CK A10/AP NC A12/BC A1 A11 NC 9 VSS VSSQ DQ3 VSS NC VSS VDD ZQ VREFCA BA1 A4 A6 A8 10 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC 11 NC A B C D E F G H J K L M N Note : Green NC balls (A1, A11, N1 and N11) indicate mechanical support balls with no internal connection. 1 2 3 4 5 6 7 8 9 10 11 Ball Locations (x4) A B C Populated ball Ball not populated D E F G H Top view (See the balls through the package) J K L M N Page 6 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM 3.2 x8 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls) 1 A B C D E F G H J K L M N NC NC 2 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 3 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 4 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 5 6 7 8 NU/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 NC 9 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 10 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC 11 NC A B C D E F G H J K L M N Note : Green NC balls (A1, A11, N1 and N11) indicate mechanical support balls with no internal connection. Ball Locations (x8) 1 A B C D E F G H J K L M N 2 3 4 5 6 7 8 9 10 11 Populated ball Ball not populated Top view (See the balls through the package) Page 7 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM 3.3 x16 Package Pinout (Top view) : 100ball FBGA Package(96balls + 4 balls of support balls) 1 A B C D E F G H J K L M N P R T NC NC 2 VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 3 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 4 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 NC 5 6 7 8 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP NC A12/BC A1 A11 NC 9 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 10 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 11 NC A B C D E F G H J K L M N P R NC T Note : Green NC balls (A1, A11, T1 and T11) indicate mechanical support balls with no internal connection. 1 A 2 3 4 5 6 7 8 9 10 11 Ball Locations (x16) B C D E Populated ball Ball not populated F G H J K Top view (See the balls through the package) L M N P R T Page 8 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM 3.4 FBGA Package Dimension (x4/x8) Units : Millimeters A #A1 INDEX MARK B 9.00 0.10 0.80 x 10 = 8.00 (Datum A) 0.80 1.60 4.00 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N (0.95) MOLDING AREA (1.90) 4.80 0.80 (Datum B) 0.80 x 12 = 9.60 82 - 0.45 Solder ball (Post Reflow 0.50 0.05) 0.2 M A B BOTTOM VIEW 0.80 11.00 0.10 #A1 9.00 0.10 11.00 0.10 0.10MAX 0.35 0.05 1.10 0.10 TOP VIEW Page 9 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM 3.5 FBGA Package Dimension (x16) Units : Millimeters A #A1 INDEX MARK 0.80 1.60 4.00 B 9.00 0.10 0.80 x 10 = 8.00 11 10 9 8 7 6 5 4 3 2 1 (Datum A) A B C D E F G H J K L M N P R T (0.95) MOLDING AREA (1.90) (Datum B) 6.00 0.80 x 15 = 12.00 0.40 100 - 0.45 Solder ball (Post Reflow 0.50 0.05) 0.2 M A B BOTTOM VIEW 0.80 13.30 0.10 #A1 9.00 0.10 13.30 0.10 0.10MAX 0.35 0.05 1.10 0.10 TOP VIEW Page 10 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 4.0 Input/Output Functional Description [ Table 3 ] Input/Output function description Symbol CK, CK Type Input Function 1Gb DDR3 SDRAM Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below) The address inputs also provide the op-code during Mode Register Set commands. Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. Data Input/ Output: Bi-directional data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/ x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. No Connect: No internal electrical connection is present. DQ Power Supply: 1.5V +/- 0.075V DQ Ground Power Supply: 1.5V +/- 0.075V Ground Reference voltage for DQ Reference voltage for CA Reference Pin for ZQ calibration CKE Input CS Input ODT Input RAS, CAS, WE DM (DMU), (DML) Input Input BA0 - BA2 Input A0 - A13 Input A10 / AP Input A12 / BC Input RESET DQ Input Input/Output DQS, (DQS) Input/Output TDQS, (TDQS) Output NC VDDQ VSSQ VDD VSS VREFDQ VREFCA ZQ Supply Supply Supply Supply Supply Supply Supply Note : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination. Page 11 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 5.0 DDR3 SDRAM Addressing 1Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 1Gb DDR3 SDRAM 256Mb x 4 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9,A11 A12/BC 1 KB 128Mb x 8 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9 A12/BC 1 KB 64Mb x 16 8 BA0 - BA2 A10/AP A0 - A12 A0 - A9 A12/BC 2 KB 2Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 512Mb x 4 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9,A11 A12/BC 1 KB 256Mb x 8 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9 A12/BC 1 KB 128Mb x 16 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9 A12/BC 2 KB 4Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 1Gb x 4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 1 KB 512Mb x 8 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9 A12/BC 1 KB 256Mb x 16 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9 A12/BC 2 KB 8Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 2Gb x 4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11,A13 A12/BC 2 KB 1Gb x 8 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 2 KB 512Mb x 16 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9 A12/BC 2 KB Note 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG/8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Page 12 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 6.0 Absolute Maximum Ratings 6.1 Absolute Maximum DC Ratings [ Table 4 ] Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -55 to +100 1Gb DDR3 SDRAM Units V V V C Notes 1,3 1,3 1 1, 2 Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 6.2 DRAM Component Operating Temperature Range [ Table 5 ] Temperature Range Symbol TOPER Parameter Operating Temperature Range rating 0 to 95 Unit C Notes 1, 2, 3 Note : 1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions 3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b) 7.0 AC & DC Operating Conditions 7.1 Recommended DC operating Conditions (SSTL_1.5) [ Table 6 ] Recommended DC Operating Conditions Symbol VDD VDDQ Supply Voltage Supply Voltage for Output Parameter Rating Min. 1.425 1.425 Typ. 1.5 1.5 Max. 1.575 1.575 Units V V Notes 1,2 1,2 Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Page 13 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 8.0 AC & DC Input Measurement Levels 8.1 AC and DC Logic input levels for single-ended signals [ Table 7 ] Single Ended AC and DC input levels for Command and Address Symbol VIH.CA(DC) VIL.CA(DC) VIH.CA(AC) VIL.CA(AC) Parameter DC input logic high DC input logic low AC input logic high AC input logic low DDR3-800/1066 Min. VREF + 100 VSS VREF + 175 0.49*VDD Max. VDD VREF - 100 VREF - 175 0.51*VDD 1Gb DDR3 SDRAM DDR3-1333/1600 Min. VREF + 100 VSS VREF + 175 VREF+150 0.49*VDD Max. VDD VREF - 100 VREF - 175 VREF-150 0.51*VDD Unit mV mV mV mV mV mV V Notes 1 1 1,2 1,2 1,2 1,2 3,4 VIH.CA(AC150) AC input logic high VIL.CA(AC150) AC input logic lowM VREFCA(DC) Reference Voltage for ADD, CMD inuts Note : 1. For input only pins except RESET, VREF = VREFCA(DC) 2. See 9.6 "Overshoot and Undershoot specifications" 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference : approx. 15mV) 4. For reference : approx. VDD/2 15mV [ Table 8 ] Single Ended AC and DC input levels for DQ and DM Symbol VIH.DQ(DC) VIL.DQ(DC) VIH.DQ(AC) VIL.DQ(AC) VREFDQ(DC) Parameter DC input logic high DC input logic low AC input logic high AC input logic low I/O Reference Voltage(DQ) DDR3-800/1066 Min. VREF + 100 VSS VREF + 175 0.49*VDD Max. VDD VREF - 100 VREF - 175 0.51*VDD DDR3-1333/1600 Min. VREF + 100 VSS VREF + 150 0.49*VDD Max. VDD VREF - 100 VREF - 150 0.51*VDD Unit mV mV mV mV V Notes 1 1 1,2,5 1,2,5 3,4 Note : 1. For input only pins except RESET, VREF = VREFDQ(DC) 2. See "Overshoot and Undershoot specifications" 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference : approx. 15mV) 4. For reference : approx. VDD/2 15mV 5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing for DQS - DQS is 700mV (peak to peak). Page 14 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 8.2 VREF Tolerances 1Gb DDR3 SDRAM The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in table 7. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than 1% VDD. voltage VDD VSS time Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 1. This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. Page 15 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 8.3 AC and DC Logic Input Levels for Ditterential Signals 8.3.1 Differential signal definition tDVAC VIH.DIFF.AC.MIN Differential Input Voltage (i.e. DQS-DQS, CK-CK) 1Gb DDR3 SDRAM VIH.DIFF.MIN 0.0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Figure 2 : Definition of differential ac-swing and "time above ac level" tDVAC 8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) [ Table 9 ] Differential AC and DC Input Levels Symbol VIHdiff VILdiff VIHdiff(AC) VILdiff(AC) Parameter differential input high differential input low differential input high ac differential input low ac DDR3-800/1066/1333/1600 min +0.2 note 3 2 x (VIH(AC)-VREF) note 3 max note 3 -0.2 note 3 2 x (VREF - VIL(AC)) unit V V V V Note 1 1 2 2 Notes: 1. Used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Reter to "overshoot and Undersheet Specification " [ Table 10 ] Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS. Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max - Page 16 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 8.3.3 Single-ended requirements for differential signals 1Gb DDR3 SDRAM Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle preceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ's might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK . VDD or VDDQ VSEH min VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max VSEL time Figure 3 : Single-ended requirement for differential signals. VSS or VSSQ Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode charateristics of these signals. [ Table 11 ] Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU Symbol VSEH VSEL Parameter Single-ended high-level for strobes Single-ended high-level for CK, CK Single-ended low-level for strobes Single-ended low-level for CK, CK DDR3-800/1066/1333/1600 Min (VDD/2)+0.175 (VDD/2)+0.175 Note3 Note3 Max Note3 Note3 (VDD/2)-0.175 (VDD/2)-0.175 Unit V V V V Notes 1, 2 1, 2 1, 2 1, 2 Notes: 1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification" Page 17 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 8.4 Differential Input Cross Point Voltage 1Gb DDR3 SDRAM To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSS Figure 4. VIX Definition [ Table 12 ] Cross point voltage for differential input signals (CK, DQS) Symbol VIX VIX Parameter Differential Input Cross Point Voltage relative to VDD/2 for CK,CK Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS DDR3-800/1066/1333/1600 Min -150 -175 -150 Max 150 175 150 Unit mV mV mV 1 Notes Note : 1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 =/-250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to table 11 on page 17 for VSEL and VSEH standard values. 8.5 Slew Rate Definition for Single Ended Input Signals See 14.3 "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See 14.4 "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.tDH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF 8.6 Slew rate definition for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5. [ Table 13 ] Differential input slew rate definition Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Measured From VILdiffmax VIHdiffmin To VIHdiffmin VILdiffmax Defined by VIHdiffmin - VILdiffmax Delta TRdiff VIHdiffmin - VILdiffmax Delta TFdiff Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds VIHdiffmin 0 VILdiffmax delta TFdiff delta TRdiff Figure 5. Differential Input Slew Rate definition for DQS, DQS and CK, CK Page 18 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 9.0 AC and DC Output Measurement Levels 9.1 Single Ended AC and DC Output Levels [ Table 14 ] Single Ended AC and DC output levels Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) 1Gb DDR3 SDRAM DDR3-800/1066/1333/1600 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ Units V V V V V Notes 1 1 Note : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT=VDDQ/2. 9.2 Differential AC and DC Output Levels [ Table 15 ] Differential AC and DC output levels Symbol VOHdiff(AC) VOLdiff(DC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3-800/1066/1333/1600 +0.2 x VDDQ -0.2 x VDDQ Units V V Notes 1 1 Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT=VDDQ/2 at each of the differential outputs. 9.3.Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 16 and figure 6. [ Table 16 ] Single Ended Output slew rate definition Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Measured From VOL(AC) VOH(AC) To VOH(AC) VOL(AC) Defined by VOH(AC)-VOL(AC) Delta TRse VOH(AC)-VOL(AC) Delta TFse Note : Output slew rate is verified by design and characterization, and may not be subject to production test. [ Table 17 ] Single Ended Output slew rate Parameter Single ended output slew rate Symbol SRQse DDR3-800 Min 2.5 Max 5 DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 DDR3-1600 Min TBD Max 5 Units V/ns Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output se : Singe-ended Signals For Ron = RZQ/7 setting VOH(AC) VTT VOL(AC) delta TFse delta TRse Figure 6. Single Ended Output Slew Rate definition Page 19 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 9.4 Differential Output Slew Rate 1Gb DDR3 SDRAM With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown inTable 18 and figure 7. [ Table 18 ] Differential Output slew rate definition Description Differential output slew rate for rising edge Differential output slew rate for falling edge Measured From VOLdiff(AC) VOHdiff(AC) To VOHdiff(AC) VOLdiff(AC) Defined by VOHdiff(AC)-VOLdiff(AC) Delta TRdiff VOHdiff(AC)-VOLdiff(AC) Delta TFdiff Note : Output slew rate is verified by design and characterization, and may not be subject to production test. [ Table 19 ] Differential Output slew rate Parameter Differential output slew rate Symbol SRQse DDR3-800 Min 5 Max 10 DDR3-1066 Min 5 Max 10 DDR3-1333 Min 5 Max 10 DDR3-1600 Min TBD Max 10 Units V/ns Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output diff : Singe-ended Signals For Ron = RZQ/7 setting VOHdiff(AC) VTT VOLdiff(AC) delta TFdiff delta TRdiff Figure 7. Differential Output Slew Rate definition 9.5 Reference Load for AC Timing and Output Slew Rate Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment of a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK/CK DUT DQ DQS DQS VTT = VDDQ/2 25 Reference Point Figure 8. Reference Load for AC Timing and Output Slew Rate Page 20 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 9.6 Overshoot/Undershoot Specification 9.6.1 Address and Control Overshoot and Undershoot specifications 1Gb DDR3 SDRAM [ Table 20 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 9) Maximum peak amplitude allowed for undershoot area (See Figure 9) Maximum overshoot area above VDD (See Figure 9) Maximum undershoot area below VSS (See Figure 9) Specification DDR3-800 0.4V 0.4V 0.67V-ns 0.67V-ns DDR3-1066 0.4V 0.4V 0.5V-ns 0.5V-ns DDR3-1333 0.4V 0.4V 0.4V-ns 0.4V-ns DDR3-1600 0.4V 0.4V 0.33V-ns 0.33V-ns Unit V V V-ns V-ns Maximum Amplitude Overshoot Area Volts (V) VDD VSS Maximum Amplitude Time (ns) Undershoot Area Figure 9. Address and Control Overshoot and Undershoot definition 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications [ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 11) Maximum peak amplitude allowed for undershoot area (See Figure 11) Maximum overshoot area above VDDQ (See Figure 11) Maximum undershoot area below VSSQ (See Figure 11) Specification DDR3-800 0.4V 0.4V 0.25V-ns 0.25V-ns DDR3-1066 0.4V 0.4V 0.19V-ns 0.19V-ns DDR3-1333 0.4V 0.4V 0.15V-ns 0.15V-ns DDR3-1600 0.4V 0.4V 0.13V-ns 0.13V-ns Unit V V V-ns V-ns Maximum Amplitude Overshoot Area Volts (V) VDDQ VSSQ Maximum Amplitude Time (ns) Undershoot Area Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot definition Page 21 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 9.7 34 ohm Output Driver DC Electrical Characteristics 1Gb DDR3 SDRAM A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ as follows: RON34 = RZQ/7 (Nominal 34ohms +/- 10% with nominal RZQ=240ohm) RON40 = RZQ/6 (Nominal 40ohms +/- 10% with nominal RZQ=240ohm) The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows RONpu = VDDQ-VOUT l Iout l VOUT l Iout l under the condition that RONpu is turned off under the condition that RONpd is turned off RONpd = Output Driver : Definition of Voltages and Currents Output Driver VDDQ Ipu To other circuity RON Pu DQ RON Ipd Iout Vout VSSQ Pd Figure 11. Output Driver : Definition of Voltages and Currents [ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240 ohms ; entire operating temperature range; after proper ZQ calibration RONnom Resistor Vout VOLdc = 0.2 x VDDQ RON34pd 34Ohms RON34pu VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ RON40pd 40Ohms RON40pu VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ Mismatch between Pull-up and Pull-down, MMpupd VOMdc = 0.5 x VDDQ Min 0.6 0.9 0.9 0.9 0.9 0.6 0.6 0.9 0.9 0.9 0.9 0.6 -10 Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 1.1 1.1 1.4 1.4 1.1 1.1 1.1 1.1 1.4 1.4 1.1 1.1 10 % RZQ/6 RZQ/7 Units Notes 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,4 Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ 4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ: MMpupd = RONpu - RONpd RONnom x 100 Page 22 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 9.7.1 Output Drive Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to table 23 and 24. T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ *dRONdT and dRONdV are not subject to production test but are verified by design and characterization [ Table 23 ] Output Driver Sensitivity Definition Min RONPU@VOHDC RON@VOMDC RONPD@VOLDC 0.6 - dRONdTH * |T| - dRONdVH * |V| 0.9 - dRONdTM * |T| - dRONdVM * |V| 0.6 - dRONdTL * |T| - dRONdVL * |V| Max 1Gb DDR3 SDRAM Units RZQ/7 RZQ/7 RZQ/7 1.1 + dRONdTH * |T| + dRONdVH * |V| 1.1 + dRONdTM * |T| + dRONdVM * |V| 1.1 + dRONdTL * |T| + dRONdVL * |V| [ Table 24 ] Output Driver Voltage and Temperature Sensitivity Speed Bin Min dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH 0 0 0 0 0 0 800/1066/1333 Max 1.5 0.15 1.5 0.15 1.5 0.15 Min 0 0 0 0 0 0 1600 Max 1.5 0.13 1.5 0.13 1.5 0.13 Units %/C %/mV %/C %/mV %/C %/mV 9.8 On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register. ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as follows : VDDQ-VOUT l Iout l VOUT l Iout l under the condition that RTTpu is turned off RTTpu = under the condition that RTTpd is turned off RTTpd = On-Die Termination : Definition of Voltages and Currents Chip in Termination Mode ODT VDDQ Ipu To other circuitry like RCV, ... Iout=Ipd-Ipu Pu RTT DQ RTT Ipd Iout Pd VOUT VSSQ Figure 12. On-Die Termination : Definition of Voltages and Currents Page 23 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 9.8.1 ODT DC electrical characteristics 1Gb DDR3 SDRAM Table 26 provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80, RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines: [ Table 25 ] ODT DC Electrical characteristics, assuming RZQ=240 ohm +/- 1% entire operating temperature range; after proper ZQ calibration. MR1 (A9,A6,A2) RTT RESISTOR Vout VOL(DC) 0.2XVDDQ RTT120pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (0,1,0) 120 ohm RTT120pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT120 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT60pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (0,0,1) 60 ohm RTT60pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT60 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT40pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (0,1,1) 40 ohm RTT40pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT40 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT60pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (1,0,1) 30 ohm RTT60pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT60 VIL(AC) to VIH(AC) VOL(DC) 0.2XVDDQ RTT60pd240 0.5XVDDQ VOH(DC) 0.8XVDDQ (1,0,0) 20 ohm RTT60pu240 VOL(DC) 0.2XVDDQ 0.5XVDDQ VOH(DC) 0.8XVDDQ RTT60 VIL(AC) to VIH(AC) Min 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 -5 Nom 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 5 Unit RZQ RZQ RZQ RZQ RZQ RZQ RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 % Notes 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,5,6 Deviation of VM w.r.t VDDQ/2, VM Page 24 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2XVDDQ and 0.8XVDDQ. 4. Not a specification requirement, but a design guide line 5. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) perspectively RTT = VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC)) 6. Measurement definition for VM and VM : Measure voltage (VM) at test pin (midpoint) with no load VM = 2 x VM VDDQ -1 x 100 9.8.2 ODT Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to table below T = T - T(@calibration); V = VDDQ - VDDQ (@calibration); VDD = VDDQ [ Table 26 ] ODT Sensitivity Definition Min RTT 0.9 - dRTTdT * |T| - dRTTdV * |V| Max 1.6 + dRTTdT * |T| + dRTTdV * |V| Units RZQ/2,4,6,8,12 [ Table 27 ] ODT Voltage and Temperature Sensitivity Min dRTTdT dRTTdV 0 0 Max 1.5 0.15 Units %/C %/mV These parameters may not be subject to production test. They are verified by design and characterization. Page 25 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 9.9 ODT Timing Definitions 9.9.1 Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in Figure 13. 1Gb DDR3 SDRAM VDDQ CK,CK DUT DQ, DM DQS , DQS TDQS , TDQS VTT= VSSQ RTT =25 ohm VSSQ Timing Reference Points Figure 13. ODT Timing Reference Load 9.9.2 ODT Timing Definition Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided in Table 29. [ Table 28 ] ODT Timing Definitions Symbol tAON tAONPD tAOF tAOFPD tADC Begin Point Definition Rising edge of CK - CK defined by the end point of ODTLon Rising edge of CK - CK with ODT being first registered high Rising edge of CK - CK defined by the end point of ODTLoff Rising edge of CK - CK with ODT being first registered low Rising edge of CK - CK defined by the end point of ODTLcnw, ODTLcwn4 of ODTLcwn8 End Point Definition Extrapolated point at VSSQ Extrapolated point at VSSQ End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively Figute Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 [ Table 29 ] Reference Settings for ODT Timing Measurements Measured Parameter tAON tAONPD tAOF tAOFPD tADC RTT_Nom Setting RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/12 RTT_Wr Setting NA NA NA NA NA NA NA NA RZQ/2 VSW1[V] 0.05 0.10 0.05 0.10 0.05 0.10 0.05 0.10 0.20 VSW2[V] 0.10 0.20 0.10 0.20 0.10 0.20 0.10 0.20 0.30 Note Page 26 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D Begin point : Rising edge of CK - CK defined by the end point of ODTLon 1Gb DDR3 SDRAM CK VTT CK tAON TSW2 DQ, DM DQS , DQS TDQS , TDQS TSW1 VSW2 VSW1 VSSQ VSSQ End point Extrapolated point at VSSQ Figure 14. Definition of tAON Begin point : Rising edge of CK - CK with ODT being first registered high CK VTT CK tAONPD TSW2 DQ, DM DQS , DQS TDQS , TDQS TSW1 VSW2 VSW1 VSSQ VSSQ End point Extrapolated point at VSSQ Figure 15. Definition of tAONPD Begin point : Rising edge of CK - CK defined by the end point of ODTLoff CK VTT CK tAOF VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS End point Extrapolated point at VRTT_Nom TSW2 VSW2 VSW1 TSW1 VSSQ TD_TAON_DEF Figure 16. Definition of tAOF Page 27 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D Begin point : Rising edge of CK - CK with ODT being first registered low 1Gb DDR3 SDRAM CK VTT CK tAOFPD VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS End point Extrapolated point at VRTT_Nom TSW2 VSW2 VSW1 TSW1 VSSQ Figure 17. Definition of tAOFPD Begin point : Rising edge of CK - CK defined by the end point of ODTLcnw Begin point : Rising edge of CK - CK defined by the end point of ODTLcwn4 or ODTLcwn8 CK VTT CK tADC tADC VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS End point Extrapolated point at VRTT_Nom VRTT_Nom TSW21 End point Extrapolated point TSW11 at VRTT_Nom VSW1 VSW2 TSW22 TSW12 VRTT_Wr End point Extrapolated point at VRTT_Wr VSSQ Figure 18. Definition of tADC Page 28 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 10.0 Idd Specification Parameters and Test Conditions 10.1 IDD Measurement Conditions 1Gb DDR3 SDRAM In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and IDDQ measurements. - IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. - IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply : - "0" and "LOW" is defined as VIN <= VILAC(max). - "1" and "HIGH" is defined as VIN >= VIHAC(min). - "FLOATING" is defined as inputs are VREF = VDD / 2. - Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 30. - Basic IDD and IDDQ Measurement Conditions are described in Table 31. - Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 33 through Table 39. - IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 - Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. - Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW} - Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH} 10.2 IDD Specifications definition Timing parameters are listed in the following table: [ Table 30 ] For IDD testing the following parameters are utilized. Parameter tCKmin(IDD) CL(IDD) tRCDmin(IDD) tRCmin(IDD) tRASmin(IDD) tRPmin(IDD) tFAW(IDD) tRRD(IDD) x4/x8 x16 x4/x8 x16 5 16 20 4 4 36 44 64 120 140 5 5 20 15 6 6 Bin DDR3-800 5-5-5 2.5 6 6 21 6 6 26 6-6-6 DDR3-1066 6-6-6 7-7-7 1.875 7 7 27 20 7 20 27 4 6 48 59 86 160 187 8 7 8 20 30 4 5 60 74 107 200 234 8 8 28 7 7 31 8 8 32 24 9 10 8 9 24 32 5 6 72 88 128 240 280 8-8-8 7-7-7 DDR3-1333 8-8-8 9-9-9 1.5 9 9 33 10 10 34 8 8 36 9 9 37 28 10 11 10-10-10 8-8-8 DDR3-1600 9-9-9 10-10-10 1.25 10 10 38 11 11 39 11-11-11 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK tRFC(IDD) - 512Mb tRFC(IDD) - 1Gb tRFC(IDD) - 2Gb tRFC(IDD) - 4Gb tRFC(IDD) - 8Gb Page 29 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [ Table 31] Basic IDD and IDDQ Measurement Conditions. Symbol Description 1Gb DDR3 SDRAM IDD0 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table32); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 32 Operating One Bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table33); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 33 Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 34 Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 35 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 35 ; Pattern Details: see Table 35 Precharge Standby ODT IDDQ Current Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 34 Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 36 ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 10); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 36 Operating Burst Read IDDQ Current Same definition like for IDD4R, however measuring IDDQ current instead of IDD current Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 37 ; Data IO: seamless write data burst with different data between one burst and the next one according to Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 37 Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 ; BL: 8a); AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially toggling according to Table 38 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 38 Self Refresh Current: Normal Temperature Range TCASE: 0 - 85C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING IDD1 IDD2N DD2NT DDQ2NT (optional) IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R (optional) IDD4W IDD5B IDD6 Page 30 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [Table 31] Basic IDD and IDDQ Measurement Conditions. Symbol Description 1Gb DDR3 SDRAM IDD6ET Self-Refresh Current: Extended Temperature Range (optional)f) TCASE: 0 - 95C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Extendede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Auto Self-Refresh Current (optional)f) TCASE: 0 - 95C; Auto Self-Refresh (ASR): Enabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 ; BL: 8a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table 39 ; Data IO: read data bursts with different data between one burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 39 IDD6TC IDD7 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 10.2 IDD and IDDQ Specifications Editorial Instruction: Chapter 10.2 in JESD79-3B in principal stays at it is. See Reference Material at the end of this ballot. Only the following changes will be done to Chapter 10.2: Table 53 "IDD Specification Example 512M DDR3", add the following Rows: - Between IDD2N and IDD2Q: Add 2 rows (one for x4/x8, one for x16) with a straddled cell for Symbol "IDD2NT". - Between IDD2NT (as inserted with above bullet) and IDD2Q: Add 2 rows (one for x4/x8, one for x16) with a straddled cell for Symbol 'IDDQ2NT". - Between IDD4R and IDD4W: Add 3 rows (one for x4, one for x8 and one for x16) with a straddled cell for Symbol "IDDQ4R". Page 31 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D (optional) 1Gb DDR3 SDRAM IDD IDDQ VDD RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ VDDQ DQS, DQS DQ, DM, TDQS, TDQS RTT = 25 Ohm VDDQ/2 VSS VSSQ Figure 19 : Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above ] Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Measurement Correlation Correction Channel IO Power Number Figure 20 :Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement. Page 32 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM [Table 32] IDD0 Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK Data2) A[9:7] A[6:3] A[2:0] 0 0 0 0 0 0 0 0 A[10] 0 0 0 0 0 0 0 0 ODT 0 0 0 0 0 0 0 0 CKE RAS CAS WE 1 0 1 0 1 0 1 0 CS 0 1 1 0 0 1 1 0 0 0 1,2 3,4 ... nRAS ... 1*nRC + 0 1*nRC + 1, 2 ACT D, D D, D PRE ACT D, D D, D PRE 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 F F F F repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary Static High toggling 1*nRC + 3, 4 ... 1*nRC + nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead Note 1. DM must be driben LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. Page 33 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [Table 33] IDD1 Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK 1Gb DDR3 SDRAM 0 0 1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC + 1, 2 ACT D, D D, D RD PRE ACT D, D D, D RD PRE 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F F F 0 0 0 0 0 0 0 0 0 0 repeat pattern 1...4 until nRCD- 1, truncate if necessary 00000000 00110011 repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary Static High toggling 1*nRC + 3, 4 ... 1*nRC + nRCD ... 1*nRC + nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. [Table 34] IDD2 and IDD3N Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK Data2) A[9:7] A[6:3] A[2:0] A[10] CKE RAS CAS ODT WE CS 0 0 1 2 3 D D D D 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 00 00 00 00 0 0 0 0 0 0 0 0 0 0 F F 0 0 0 0 Static High toggling 1 2 3 4 5 6 7 4-7 8-11 12-15 16-19 20-23 24-27 28-31 repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead Note : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. Page 34 of 60 Rev. 1.1 August 2008 Data2) - A[9:7] A[6:3] A[2:0] A[10] CKE RAS CAS ODT WE CS K4B1G04(08/16)46D [Table 35] IDD2NT and IDDQ2NT Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK 1Gb DDR3 SDRAM 0 0 1 2 3 D D D D 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 00 00 00 00 0 0 0 0 0 0 0 0 0 0 F F 0 0 0 0 Static High toggling 1 2 3 4 5 6 7 4-7 8-11 12-15 16-19 20-23 24-27 28-31 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 7 Note : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. [Table 36] IDD4R and IDDQ4R Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK Data2) 00000000 00110011 A[9:7] A[6:3] A[2:0] A[10] CKE RAS CAS ODT WE CS 0 0 1 2,3 4 5 RD D D,D RD D D,D 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F 0 0 0 0 0 0 Static High toggling 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7 Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. Page 35 of 60 Rev. 1.1 August 2008 Data2) - A[9:7] A[6:3] A[2:0] A[10] CKE RAS CAS ODT WE CS K4B1G04(08/16)46D 1Gb DDR3 SDRAM [Table 37] IDD4W Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK Data2) 00000000 00110011 Data2) A[9:7] A[6:3] 0 0 0 F F F A[6:3] 0 0 F A[2:0] 0 0 0 0 0 0 A[2:0] 0 0 0 A[10] 0 0 0 0 0 0 A[10] 0 0 0 ODT 1 1 1 1 1 1 CKE RAS CAS 0 0 1 0 0 1 WE 0 0 1 0 0 1 CS 0 1 1 0 1 1 0 0 1 2,3 4 5 WR D D,D WR D D,D 1 0 1 1 0 1 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 0 Static High toggling 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7 Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. [Table 38] IDD5B Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK A[9:7] 0 0 0 CKE RAS CAS ODT 0 0 0 WE 1 0 1 CS 0 1 1 0 1 0 1,2 3,4 5...8 REF D D,D 0 0 1 0 0 1 0 0 0 00 00 00 repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. Static High toggling 9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC - 1 Note : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. Page 36 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [Table 39] IDD7 Measurement - Loop Pattern1 Command Sub-Loop A[15:11] Cycle Number BA[2:0] CK/CK 1Gb DDR3 SDRAM 0 0 1 2 ... nRRD 1 nRRD + 1 nRRD + 2 ... 2 3 4 5 6 7 8 Static High toggling 9 2 * nRRD 3 * nRRD 4 * nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 10 2*nFAW+1 2*nFAW+2 2*nFAW+nRRD 11 2*nFAW+nRRD+1 2*nFAW+nRRD+2 12 13 14 15 16 17 18 19 2*nFAW+2*nRRD 2*nFAW+3*nRRD 2*nFAW+4*nRRD 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 3*nFAW+4*nRRD ACT RDA D ACT RDA D 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 00 00 00 00 00 00 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 F F F 0 0 0 0 0 0 00000000 00110011 - repeat above D Command until nRRD - 1 repeat above D Command until nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7 D ACT RDA D ACT RDA D 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 7 0 0 0 1 1 1 00 00 00 00 00 00 00 0 0 1 0 0 1 0 0 0 0 0 0 0 0 F F F F 0 0 0 0 0 0 0 0 0 0 00110011 00000000 Assert and repeat above D Command until 2*nFAW - 1, if necessary Repeat above D Command until 2*nFAW + nRRD - 1 Repeat above D Command until 2*nFAW + 2*nRRD - 1 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 0 0 Assert and repeat above D Command until 3*nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 0 0 Assert and repeat above D Command until 4*nFAW - 1, if necessary Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otheerwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL. Page 37 of 60 Rev. 1.1 August 2008 Data2) - A[9:7] A[6:3] A[2:0] A[10] CKE RAS CAS ODT WE CS K4B1G04(08/16)46D 11.0 1Gb DDR3 SDRAM D-die IDD Spec Table [ Table 40 ] IDD Specification for 1Gb DDR3 D-die 256Mx4 (K4B1G0446D) Symbol IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2NT IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 DDR3-800 6-6-6 75 95 10 35 50 55 45 40 50 115 125 205 10 240 DDR3-1066 7-7-7 85 105 11 45 55 65 55 45 60 155 160 210 10 265 DDR3-1333 9-9-9 90 110 12 50 60 70 60 50 65 185 190 220 10 340 1Gb DDR3 SDRAM DDR3-1600 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes 128Mx8 (K4B1G0846D) Symbol IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2NT IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 DDR3-800 6-6-6 75 95 10 35 50 55 45 40 50 135 145 205 10 245 DDR3-1066 7-7-7 85 105 11 45 55 65 55 45 60 170 190 210 10 275 DDR3-1333 9-9-9 90 110 12 50 60 75 60 50 65 205 230 220 10 365 DDR3-1600 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit Notes Page 38 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [ Table 40] IDD Specification for 1Gb DDR3 D-die(Cont.) 64Mx16 (K4B1G1646D) Symbol IDD0 IDD1 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2NT IDD2Q IDD3P(fast exit) IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 DDR3-800 6-6-6 85 120 10 35 50 50 45 40 50 180 185 205 10 280 DDR3-1066 7-7-7 90 125 11 45 55 55 55 45 60 230 235 210 10 310 DDR3-1333 9-9-9 100 135 12 50 60 60 60 50 65 290 290 220 10 370 1Gb DDR3 SDRAM DDR3-1600 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes Page 39 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 12.0 Input/Output Capacitance [ Table 41 ] Input / Output Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) Input capacitance delta (CK and CK) Input capacitance (All other input-only pins) Input capacitance delta (DQS and DQS) Input capacitance delta (All control input-only pins) Input capacitance delta (all ADD and CMD input-onlypins) Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS) Input/output capacitance of ZQ pin Symbol CIO CCK CDCK CI CDDQS CDI_CTRL CDI_ADD_CMD CDIO CZQ DDR3-800 Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 3.0 1.6 0.15 1.5 0.2 0.3 0.5 0.3 3 DDR3-1066 Min 1.5 0.8 0 0.75 0 -0.5 -0.5 -0.5 Max 2.7 1.6 0.15 1.5 0.2 0.3 0.5 0.3 3 DDR3-1333 Min 1.5 0.8 0 0.75 0 -0.4 -0.4 -0.5 - 1Gb DDR3 SDRAM DDR3-1600 Min 1.5 0.8 0 0.75 0 -0.4 -0.4 -0.5 Max 2.3 1.4 0.15 1.3 0.15 0.2 0.4 0.3 3 Max 2.5 1.4 0.15 1.3 0.15 0.2 0.4 0.3 3 Units pF pF pF pF pF pF pF pF pF Notes 1,2,3 2,3 2,3,4 2,3,6 2,3,5 2,3,7,8 2,3,9,10 2,3,11 2, 3, 12 Note : 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK 5. Absolute value of CIO(DQS)-CIO(DQS) 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTRL applies to ODT, CS and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance on ZQ pin: 5pF Page 40 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM 13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 13.1 Clock specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3 SDRAM device. 13.1.1 Definition for tCK (avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. tCKj j=1 N N N=200 13.1.2 Definition for tCK (abs) tCK(abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test. 13.1.3 Definition for tCH(avg) and tCL(avg) tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: j=1 N tCHj N x tCK(avg) N=200 tCLj j=1 N N x tCK(avg) N=200 13.1.4 Definition for note for tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not subject to production test. 13.1.5 Definition for tJIT(cc), tJIT(cc,lck) tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi} tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not subject to production test. 13.1.6 Definition for tERR(nper) tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test. Page 41 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 13.2 Refresh Parameters by Device Density [ Table 42 ] Refresh parameters by device density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval tREFI Symbol tRFC 0 C TCASE 85C 85 C < TCASE 95C 1Gb 110 7.8 3.9 2Gb 160 7.8 3.9 1Gb DDR3 SDRAM 4Gb 300 7.8 3.9 8Gb 350 7.8 3.9 Units ns s s Note 1 Note : 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. 13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. [ Table 43 ] DDR3-800 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 6 / CWL = 5 Supported CL Settings Supported CWL Settings [ Table 44 ] DDR3-1066 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 6 CL = 7 CL = 8 Supported CL Settings Supported CWL Settings CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.875 6,7,8 5,6 1.875 Reserved <2.5 min 13.125 13.125 13.125 50.625 37.5 2.5 Reserved Reserved <2.5 DDR3-1066 7-7-7 max 20 9*tREFI 3.3 ns ns ns ns ns ns ns ns ns ns ns nCK nCK 8 1,2,3,6 1,2,3,4 4 1,2,3,4 4 1,2,3 Units Note Symbol tAA tRCD tRP tRC tRAS tCK(AVG) min 15 15 15 52.5 37.5 2.5 6 5 DDR3-800 6-6-6 max 20 9*tREFI 3.3 ns ns ns ns ns ns nCK nCK 8 1,2,3 Units Note Page 42 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [ Table 45] DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 5 CL = 8 CWL = 6 CWL = 7 CL = 9 CWL = 5,6 CWL = 7 CWL = 5,6 CL = 10 Supported CL Settings Supported CWL Settings CWL = 7 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 1.5 (Optional) 6,7,8,9 5,6,7 1.5 Reserved <1.875 1.875 Reserved Reserved <1.875 1.875 Reserved Reserved <2.5 min 13.5 13.5 13.5 49.5 36 2.5 Reserved Reserved Reserved <2.5 DDR3-1333 9 -9 - 9 max 20 9*tREFI 3.3 1Gb DDR3 SDRAM Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK Note 8 1,2,3,7 1,2,3,4,7 4 4 1,2,3,4,7 1,2,3,4, 4 1,2,3,7 1,2,3,4, 4 1,2,3,4 4 1,2,3 5 Page 43 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [ Table 46 ] DDR3-1600 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 7, 8 CWL = 5 CL = 7 CWL = 6 CWL = 7 CWL = 8 CWL = 5 CL = 8 CWL = 6 CWL = 7 CWL = 8 CWL = 5,6 CL = 9 CWL = 7 CWL = 8 CWL = 5,6 CL = 10 CWL = 7 CWL = 8 CWL = 5,6,7 CL = 11 Supported CL Settings Supported CWL Settings CWL = 8 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) min TBD TBD TBD TBD 35 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD DDR3-1600 TBD max 20 9*tREFI 1Gb DDR3 SDRAM Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK Note 13.3.1 Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Note : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL". 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED. 4. "Reserved" settings are not allowed. User must program a different value. 5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/ or the DIMM SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. Page 44 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 14.0 Timing Parameters by Speed Grade [ Table 47 ] Timing Parameters by Speed Bin Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14 ... 49, 50 cycles Absolute clock HIGH pulse width Absolute clock Low pulse width Data Timing DQS,DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK Data setup time to DQS, DQS referenced to VIH(AC)VIL(AC) levels Data hold time to DQS, DQS referenced to VIH(AC)VIL(AC) levels DQ and DM Input pulse width for each input Data Strobe Timing DQS, DQS READ Preamble DQS, DQS differential READ Postamble DQS, DQS output high time DQS, DQS output low time DQS, DQS WRITE Preamble DQS, DQS WRITE Postamble DQS, DQS rising edge output access time from rising CK, CK DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS,DQS faling edge setup time to CK, CK rising edge DQS,DQS faling edge hold time to CK, CK rising edge tRPRE tRPST tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH 0.9 0.3 0.38 0.38 0.9 0.3 -400 -800 0.45 0.45 -0.25 0.2 0.2 Note 19 Note 11 400 400 400 0.55 0.55 0.25 0.9 0.3 0.38 0.38 0.9 0.3 -300 -600 0.45 0.45 -0.25 0.2 0.2 Note 19 Note 11 300 300 300 0.55 0.55 0.25 0.9 0.3 0.4 0.4 0.9 0.3 -255 -500 0.45 0.45 -0.25 0.2 0.2 tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tDIPW 0.38 -800 75 150 600 200 400 400 0.38 -600 25 100 490 150 300 300 0.38 -500 30 65 400 125 250 250 tCK(DLL_OF F) tCK(avg) tCK(abs) tCH(avg) tCL(avg) tJIT(per) tJIT(per, lck) tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tERR(nper) tCH(abs) tCL(abs) 0.43 0.43 - 147 - 175 - 194 - 209 - 222 - 232 - 241 - 249 - 257 - 263 - 269 8 8 8 Symbol DDR3-800 MIN MAX DDR3-1066 MIN MAX DDR3-1333 MIN 1Gb DDR3 SDRAM DDR3-1600 MIN MAX MAX Units Note 8 - ns ps ps tCK(avg) tCK(avg) ps ps ps ps 6 See Speed Bins Table tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max 0.47 0.47 -100 -90 200 180 0.53 0.53 100 90 0.47 0.47 -90 -80 180 160 0.53 0.53 90 80 0.47 0.47 -80 -70 160 140 0.53 0.53 80 70 0.47 0.47 -70 -60 140 120 0.53 0.53 70 60 147 175 194 209 222 232 241 249 257 263 269 - 132 - 157 - 175 - 188 - 200 - 209 - 217 - 224 - 231 - 237 - 242 132 157 175 188 200 209 217 224 231 237 242 - 118 - 140 - 155 - 168 - 177 - 186 - 193 - 200 - 205 - 210 - 215 118 140 155 168 177 186 193 200 205 210 215 -103 -122 -136 -147 -155 -163 -169 -175 -180 -184 -188 103 122 136 147 155 163 169 175 180 184 188 ps ps ps ps ps ps ps ps ps ps ps ps 24 25 26 tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max 0.43 0.43 0.43 0.43 0.43 0.43 - tCK(avg) tCK(avg) 0.38 -450 10 45 360 100 225 225 ps tCK(avg) ps ps ps ps ps 13 13, g 13,14, f 13,14, f d, 17 d, 17 28 - - - Note 19 Note 11 255 250 250 0.55 0.55 0.25 - 0.9 0.3 0.4 0.4 0.9 0.3 -225 -450 0.45 0.45 -0.27 0.18 0.18 Note 19 Note 11 225 225 225 0.55 0.55 0.27 - tCK tCK tCK(avg) tCK(avg) tCK tCK ps ps ps tCK tCK tCK(avg) tCK(avg) tCK(avg) 13, 19, g 11, 13, b 13, g 13, g 13,f 13,14,f 12,13,14 29, 31 30, 31 c c, 32 c, 32 Page 45 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM [ Table 47 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS# to CAS# command delay Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period for 1KB page size ACTIVE to ACTIVE command period for 2KB page size Four activate window for 1KB page size Four activate window for 2KB page size Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels Command and Address hold time from CK, CK referenced to VIH(AC) / VIL(AC) levels Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels Control & Address Input pulse width for each input Calibration Timing Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Reset Timing Exit Reset from CKE HIGH to a valid command Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self refresh entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tXS tXSDLL tCKESR tCKSRE tCKSRX max(5nCK,tR FC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns) max(5nCK,tR FC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns) max(5nCK,tR FC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns) max(5nCK,tR FC + 10ns) tDLLK(min) tCKE(min) + 1tCK max(5nCK, 10ns) max(5nCK, 10ns) nCK tXPR max(5nCK, tRFC + 10ns) max(5nCK, tRFC + 10ns) max(5nCK, tRFC + 10ns) max(5nCK, tRFC + 10ns) tZQinitI tZQoper tZQCS 512 256 64 512 256 64 512 256 64 512 256 64 nCK nCK nCK 23 tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRRD tRRD tFAW tFAW tIS(base) tIH(base) tIS(base) AC150 tIPW 1 1 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns ) 4 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns ) 4 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns ) 4 512 max (4nCK,7.5ns) max (4nCK,7.5ns) 15 4 max (12nCK,15ns ) 4 nCK nCK 1 nCK ns ns ns ps ps ps ps 22 e e e e e b,16 b,16 b,16,27 28 ns nCK nCK e e,18 e Symbol DDR3-800 MIN MAX DDR3-1066 MIN MAX DDR3-1333 MIN MAX DDR3-1600 MIN MAX Units Note WR + roundup (tRP / tCK(AVG)) 1 See 13.3 " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 37 max (4nCK,10ns) max (4nCK,10ns) 40 50 200 275 200 + 150 900 max (4nCK,7.5ns) max (4nCK,10ns) 37.5 50 125 200 125 + 150 780 max (4nCK,6ns) max (4nCK,7.5ns) 30 45 65 140 65+125 620 max (4nCK,6ns) max (4nCK,7.5ns) 30 40 TBD TBD TBD+125 560 - - Page 46 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM [ Table 47 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid command;Exit Percharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXP max (3nCK, 7.5ns) max (10nCK, 24ns) max (3nCK, 7.5ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL + 4 +WR +1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min) max (3nCK, 7.5ns) max (10nCK, 24ns) max (3nCK, 5.625ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL + 4 +WR +1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min) max (3nCK,6ns) max (10nCK, 24ns) max (3nCK, 5.625ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL + 4 +WR +1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min) max (3nCK,6ns) max (10nCK, 24ns) max (3nCK,5ns) 1 tCKE(min) 1 1 RL + 4 +1 WL + 4 +(tWR/ tCK(avg)) WL + 4 +WR +1 WL + 2 +(tWR/ tCK(avg)) WL +2 +WR +1 1 tMOD(min) Symbol DDR3-800 MIN MAX DDR3-1066 MIN MAX DDR3-1333 MIN MAX DDR3-1600 MIN MAX Units Note tXPDLL - - - - 2 CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of PRE command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) Timing of WR command to Power Down entry (BL4MRS) Timing of WRA command to Power Down entry (BL4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry ODT Timing ODT high time without write command or with wirte command and BC4 ODT high time with Write command and BL8 Asynchronous RTT tum-on delay (Power-Down with DLL frozen) Asynchronous RTT tum-off delay (Power-Down with DLL frozen) ODT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed DQS/DQS delay after tDQS margining mode is programmed Setup time for tDQSS latch Write leveling hold time from rising DQS, DQS crossing to rising CK, CK crossing Write leveling output delay Write leveling output error tCKE tCPDED tPD tACTPDEN tPRPDEN tRDPDEN tWRPDEN 9*tREFI - 9*tREFI - 9*tREFI - 9*tREFI nCK 9 nCK tCK nCK nCK 15 20 20 tWRAPDEN - - - - nCK 10 tWRPDEN - - - - nCK 9 tWRAPDEN tREFPDEN tMRSPDEN - - - - nCK 10 20,21 ODTH4 ODTH8 tAONPD tAOFPD tAON tAOF tADC 4 6 2 2 -400 0.3 0.3 8.5 8.5 400 0.7 0.7 4 6 2 2 -300 0.3 0.3 8.5 8.5 300 0.7 0.7 4 6 2 2 -250 0.3 0.3 8.5 8.5 250 0.7 0.7 4 6 2 2 -225 0.3 0.3 8.5 8.5 225 0.7 0.7 nCK nCK ns ns ps tCK(avg) tCK(avg) 7,f 8,f f tWLMRD tWLDQSEN tWLS tWLH tWLO tWLOE 40 25 325 325 0 0 9 2 40 25 245 245 0 0 9 2 40 25 195 195 0 0 9 2 40 25 165 165 0 0 7.5 2 tCK tCK ps ps ns ns 3 3 Page 47 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 14.1 Jitter Notes Specific Note a 1Gb DDR3 SDRAM Unit 'tCK(avg)' represents the actual tCK(avg) of the input clock under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min. Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe signal (DQS(L/U), DQS(L/U)) crossing. Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter. Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!) Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12. Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!) Page 48 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 14.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register 5. Value must be rounded-up to next higher integer value 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. For definition of RTT turn-on time tAON see "Device Operation" 8. For definition of RTT turn-off time tAOF see "Device Operation". 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer. 10. WR in clock cycles as programmed in MR0 1Gb DDR3 SDRAM 11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. Device Operation. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD 13. Value is valid for RON34 14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method. 15. tREFI depends on TOPER 16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). FOr input only pins except RESET, VREF(DC)=VREFCA(DC). See "Address/ Command Setup, Hold and Derating" 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals, VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC). See "Data Setup, Hold and Slew Rate Derating" 18. Start of internal write transaction is definited as follows ; For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL 19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation" 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Altough CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. See "Device Operation". 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the 'Output Driver Voltage and Temperature Sensitivity' and 'ODT Voltage and Temperature Sensitivity' tables. The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula: ZQCorrection (TSens x Tdriftrate) + (VSens x Vdriftrate) where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as: 0.5 (1.5 x 1) + (0.15 x 15) 24. n = from 13 cycles to 50 cycles. This row defines 38 parameters. = 0.133 ~ 128ms ~ 25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns]. 28. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC) 29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge. 30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge. 31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application. 32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application. Page 49 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 14.3 Address / Command Setup, Hold and Derating: 1Gb DDR3 SDRAM For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table 48) to the tIS and tIH derating value (see Table 49) respectively. Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(DC) to ac region', use nominal slew rate for derating value (see Figure 23). If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(DC) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 25). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded 'dc to VREF(DC) region', use nominal slew rate for derating value (see Figure 24). If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(DC) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 26). For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 50). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. [ Table 48] ADD/CMD Setup and Hold Base-Values for 1V/ns [ps] tIS(base) tIH(base) tIS(base)-AC150 DDR3-800 200 275 200 + 150 DDR3-1066 125 200 125 + 150 DDR3-1333 65 140 65+125 DDR3-1600 45 120 45+125 reference VIH/L(AC) VIH/L(DC) VIH/L(AC) Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate Note : The tIS(base)-AC150 specifications are further adjusted to add an addi-tional 100ps of derating to accommodate for the lower alternate thresh-old of 150mV and another 25ps to acccount for the earlier reference point [(175mv-150mV)/1 V/ns]. [ Table 49] Derating values DDR3-800/1066/1333/1600 tIS/tIH-ac/dc based tIS, tIH Derating [ps] AC/DC based AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CLK,CLK Differential Slew Rate 4.0 V/ns tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 3.0 V/ns tIS 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 88 59 0 -2 -6 -11 -17 -35 -62 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 96 67 8 6 2 -3 -9 -27 -54 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 104 75 16 14 10 5 -1 -19 -46 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 112 83 24 20 13 13 7 -11 -38 tIH 74 58 24 20 14 8 -2 -16 -36 1.2V/ns tIS 120 91 32 30 26 21 15 -2 -30 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 128 99 40 38 34 29 23 5 -22 tIH 100 84 50 46 40 34 24 10 -10 Page 50 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D [ Table 50 ] Derating values DDR3-1333/1600 tIS/tIH-ac/dc based - Alternate AC150 Threshold 1Gb DDR3 SDRAM tIS, tIH Derating [ps] AC/DC based Alternate AC150 Threshold -> VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CLK,CLK Differential Slew Rate 4.0 V/ns tIS 2.0 1.5 CMD/ ADD Slew rate V/ns 1.0 0.9 0.8 0.7 0.6 0.5 0.4 75 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 3.0 V/ns tIS 75 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 2.0 V/ns tIS 75 50 0 0 0 0 -1 -10 -25 tIH 50 34 0 -4 -10 -16 -26 -40 -60 1.8 V/ns tIS 83 58 8 8 8 8 7 -2 -17 tIH 58 42 8 4 -2 -8 -18 -32 -52 1.6 V/ns tIS 91 66 16 16 16 16 15 6 -9 tIH 66 50 16 12 6 0 -10 -24 -44 1.4V/ns tIS 99 74 24 24 24 24 23 14 -1 tIH 74 58 24 20 14 8 -2 -16 -36 1.2V/ns tIS 107 82 32 32 32 32 31 22 7 tIH 84 68 34 30 24 18 8 -6 -26 1.0V/ns tIS 115 90 40 40 40 40 39 30 15 tIH 100 84 50 46 40 34 24 10 -10 [ Table 51 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition Slew Rate[V/ns] min >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 < 0.5 75 57 50 38 34 29 22 13 0 0 tVAC @175mV [ps] max - tVAC @150mV [ps] min 175 170 167 163 162 161 159 155 150 150 max - Page 51 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH CK DQS DQS tDS VDDQ tDH tDS tVAC tDH VIH(AC) min VREF to ac region VIH(DC) min nominal slew rate VREF(DC) nominal slew rate VIL(DC) max VREF to ac region VIL(AC) max tVAC V SS Delta TF Setup Slew Rate= VREF(DC) - VIL(AC)max Falling Signal Delta TF Delta TR Setup Slew Rate VIH(AC)min - VREF(DC) = Rising Signal Delta TR Figure 21 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock). Page 52 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH CK DQS DQS VDDQ tDS tDH tDS tDH VIH(AC) min VIH(DC) min dc to VREF region VREF(DC) dc to VREF region VIL(DC) max nominal slew rate dc to VREF region nominal slew rate VIL(AC) max VSS Delta TR Hold Slew Rate VREF(DC) - VIL(DC)max Rising Signal = Delta TR Delta TF Hold Slew Rate VIH(DC)min - VREF(DC) Falling Signal = Delta TF Figure 22 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock). Page 53 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH CK DQS DQS VDDQ tDS tDH nominal line VREF to ac region VIH(DC) min tangent line VREF(DC) tangent line VIL(DC) max VREF to ac region VIL(AC) max nominal line VSS tDS tVAC tDH VIH(AC) min Delta TR Setup Slew Rate tangent line[VIH(AC)min - VREF(DC)] Rising Signal= Delta TR Delta TF Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max] Falling Signal = Delta TF Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock) Page 54 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH 1Gb DDR3 SDRAM CK DQS DQS tDS VDDQ tDH tDS tDH VIH(AC) min nominal line VIH(DC) min dc to VREF region VREF(DC) dc to VREF region VIL(DC) max tangent line tangent line nominal line VIL(AC) max VSS Delta TR Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] Rising Signal = Delta TR Hold Slew Rate tangent line [ VIH(DC)min - VREF(DC) ] Falling Signal = Delta TF Delta TF Figure 24 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock) Page 55 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 14.4 Data Setup, Hold and Slew Rate Derating: 1Gb DDR3 SDRAM For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see Table 52) to the tDS and tDH (see Table 53) derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max (see Figure 25). If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(DC) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(DC) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 27). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC) (see Figure 26). If the actual signal is always later than the nominal slew rate line between shaded 'dc level to VREF(DC) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(DC) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 28). For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 54). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization [ Table 52 ] Data Setup and Hold Base-Value [ps] tDS(base) tDH(base) DDR3-800 75 150 DDR3-1066 25 100 DDR3-1333 30 65 DDR3-1600 10 45 reference VIH/L(AC) VIH/L(DC) Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate) [ Table 53 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-ac/dc based tDS, tDH Derating [ps] AC/DC baseda DQS,DQS Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns tDS tDH tDS tDH tDS tDH 88 50 59 34 67 42 0 0 8 8 16 16 -2 -4 6 4 14 12 -6 -10 2 -2 10 6 -3 -8 5 0 -1 -10 75 50 50 34 58 42 0 0 8 8 16 16 0 -4 8 4 16 12 0 -10 8 -2 16 6 8 -8 16 0 15 -10 - DDR3 DQ Slew 800/ rate 1066 V/ns DDR3 DQ Slew 1333/ rate 1600 V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 4.0 V/ns tDS tDH 88 50 59 34 0 0 75 50 50 34 0 0 - 3.0 V/ns tDS tDH 88 50 59 34 0 0 -2 -4 75 50 50 34 0 0 0 -4 - 1.4V/ns tDS tDH 22 20 18 14 13 8 7 -2 -11 -16 24 20 24 14 24 8 23 -2 14 -16 - 1.2V/ns tDS tDH 26 24 21 18 15 8 -2 -6 -30 -26 32 24 32 18 31 8 22 -6 7 -26 1.0V/ns tDS tDH 29 34 23 24 6 10 -22 -10 40 34 39 24 30 10 15 -10 Note : a. Cell contents shaded in red are defined as 'not supported'. [ Table 54 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition Slew Rate[V/ns] >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 tVAC[ps] DDR3-800/1066 min 75 57 50 38 34 29 22 13 0 0 tVAC[ps] DDR3-1333/1600 min 175 170 167 163 162 161 159 155 155 150 max - max - Page 56 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH CK DQS DQS tDS VDDQ tDH tDS tVAC tDH VIH(AC) min VREF to ac region VIH(DC) min nominal slew rate VREF(DC) nominal slew rate VIL(DC) max VREF to ac region VIL(AC) max tVAC VSS Delta TF Setup Slew Rate= VREF(DC) - VIL(AC)max Falling Signal Delta TF Delta TR Setup Slew Rate VIH(AC)min - VREF(DC) = Rising Signal Delta TR Figure 25 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock). Page 57 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH 1Gb DDR3 SDRAM CK DQS DQS VDDQ tDS tDH tDS tDH VIH(AC) min VIH(DC) min dc to VREF region VREF(DC) dc to VREF region VIL(DC) max nominal slew rate dc to VREF region nominal slew rate VIL(AC) max VSS Delta TR Hold Slew Rate = Rising Signal VREF(DC) - VIL(DC)max Delta TR Delta TF VIH(DC)min - VREF(DC) Hold Slew Rate = Falling Signal Delta TF Figure 26 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock). Page 58 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH 1Gb DDR3 SDRAM CK DQS DQS VDDQ tDS tDH nominal line VREF to ac region VIH(DC) min tangent line VREF(DC) tangent line VIL(DC) max VREF to ac region VIL(AC) max nominal line VSS tDS tVAC tDH VIH(AC) min Delta TR Setup Slew Rate tangent line[VIH(AC)min - VREF(DC)] Rising Signal= Delta TR Delta TF Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max] Falling Signal = Delta TF Figure 27 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock) Page 59 of 60 Rev. 1.1 August 2008 K4B1G04(08/16)46D 1Gb DDR3 SDRAM Note :Clock and Strobe are drawn on a different time scale. tIS CK tIH tIS tIH CK DQS DQS tDS VDDQ tDH tDS tDH VIH(AC) min nominal line VIH(DC) min dc to VREF region VREF(DC) dc to VREF region VIL(DC) max tangent line tangent line nominal line VIL(AC) max VSS Delta TR Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] Rising Signal = Delta TR Hold Slew Rate tangent line [ VIH(DC)min - VREF(DC) ] Falling Signal = Delta TF Delta TF Figure 28 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock) Page 60 of 60 Rev. 1.1 August 2008 |
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